Simulation and/or emulation of an integrated circuit is a primary vehicle for design verification of an integrated circuit, particularly one that includes random logic. Typically, simulation and/or emulation of an integrated circuit is relatively expensive and time consuming. Model sizes pose severe restrictions on every form of verification be it simulation, emulation, or formal verification. For instance, simulation resource requirements are a function of the model size. In the case of large multi-processor systems, it may take months to simulate the design for all the planned test programs on a set of resources. If the model size is reduced by half then the time or the resource requirement is also reduced by 50%. This translates to significant dollar amount in savings. In some instances pre-silicon verification efforts are abandoned simply because the model size was too large for the resources to handle. Escalating complexity of modern digital designs is destined to make these problems even more acute.
There are two types of simulators, cycle simulators and event driven simulators. A cycle simulator evaluates all similar gates in the design driving each cycle. An event driven simulator, on the other hand, evaluates a portion of the logic only when triggered by an event that actually affects that logic. In event driven simulators, an event history table is needed to track the relationships of the different portions of the logic that are to be implemented. This table can become extremely large when simulating an integrated circuit that includes random logic. This table is very large in this instance because there may be many competing events happening in the integrated circuit.
Hence, typically cycle simulators are faster for most cases than event-driven simulators. However, to evaluate all gates for each cycle as is required in cycle simulators becomes very time consuming and expensive. This is particularly true, in complex designs such as multiprocessing architectures and the like.
What is needed therefore is a system that can reduce the overall expense and also increase the speed of simulating particular types of integrated circuits. In addition, the simulation system and method should be one which significantly reduces the model size by a factor over the prior art. The present invention addresses such a need.